A goal in the semiconductor industry is to reduce the size of integrated circuit device for a given functionality. One advantage of reducing device size is typically an increase in the speed of the circuit due to the quicker switching speeds of the transistors. However, as device size and distances between device components get smaller, the capacitance associated with conductors increases, causing an increase in the circuit internal RC delay, and thus slowing down the speed of the circuit.
Several layers of conductors are generally used in the active components of an integrated circuit device. The upper layers of these conductors are typically formed of metal, for example as shown in the cross-sectional view of a conventional device in FIG. 1a, at each layer metal signal lines 11, 12, 13, 14, 15, and 16 overlie an insulation layer 44. A thin layer of interlevel dielectric 7 overlies the metal signal lines and the intermetal spacings, 17, 18, 19, 20, and 21. The aspect ratio of the intermetal spacings is the ratio of the thickness of the metal signal lines surrounding the intermetal spacing to its width. As the width of the intermetal spacing is made smaller without changing the thickness of the lines, the aspect ratio of the intermetal spacing becomes larger. When the interlevel dielectric is conformal, voids 22, 23, 24, 25, and 26 may form in the interlevel dielectric between metal signal lines. At locations where the intermetal spacing is narrow and the aspect ratio of the intermetal spacings is greater than one, the voids may be sealed.
As illustrated in FIG. 1a, in the prior art most voids are not sealed. The voids 24 that are sealed only have a thin layer of interlevel dielectric sealing the void, so overetch in future process steps could open the voids and expose them to contamination. This presents problems including possible moisture or metal contamination leading to poor device performance, reduced reliability, and shortened device life. Thus, an objective in the prior art is to open all of the voids and fill them with a dielectric. A layer of spin-on-glass (SOG) or spin-on-polymer (SOP), hereinafter flowable dielectric, is usually used to fill in voids 22, 23, 25, and 26.
In the prior art, various silicon oxides, primarily SiO.sub.2, have been used as interlevel dielectrics. There is a shift to use fluorinated SiO.sub.2, which has a lower dielectric constant, as the interlevel dielectric in order to reduce interlevel capacitance. There is also experimentation in using organic spin-on-polymers as interlevel dielectrics. All of these materials have proven inadequate for today's sub-micron technologies. One problem in the prior art is that organic spin-on-polymers present problems due to etch complexity, to moisture content that can cause short circuits, and to temperature limitations that present problems in backend processing.
A further problem is that it is also now becoming disadvantageous to reduce the geometries of the integrated circuit further because, as the metal signal lines are placed closer together, the RC delay caused by the high capacitance between the lines reduces the speed of the circuit. As the distance between metal signal lines is reduced, the capacitance between the metal signal lines, hereinafter interlevel capacitance, increases. The interlevel capacitance is dependent on the ratio of the dielectric constant of the dielectric to the width of the intermetal spacing between the metal signal lines.
By way of further background, Ting et al., "A Strategy to Accelerate the Implementation of Low K ILD Materials in ULSI Interconnections", Advanced Metallization for ULSI Applications in 1994, Blumenthal et al. ed., Material Research Society, Pittsburgh, 1995, pages 351-353, describes the increase in capacitance between metal signal lines as the distance between them decreases. As shown in FIG. 1 on page 352 of this text, when the dielectric is thermal SiO.sub.2, having a dielectric constant of 3.9, the capacitance increases drastically as the distance between the metal signal lines is reduced below 0.5 .mu.m.
Thus, one way to reduce the intermetal capacitance, especially at small distances between the metal signal lines, is by using the dielectric material with a low dielectric constant. It has been observed in connection with the current invention, that using air or another atmosphere in which the integrated circuit is manufactured as an intermetal dielectric would result in lower interlevel capacitance, since air has a dielectric constant of 1. However, as can be seen in FIG. 1a, the process used in the prior art does not ensure that sealed voids would remain buried under a layer of interlevel dielectric or that all voids would be filled with flowable dielectric, presenting the possibility that a void that was at first sealed, would be opened and exposed during subsequent etch steps. Moisture or metal from the next metallization level can form in such an opened and exposed void, causing shorts, corrosion, metal step coverage problems, or via poisoning. It is therefore necessary to ensure that the voids formed are either all filled with flowable dielectric or that the sealed voids remain sealed, as according to the present invention. This is difficult to ensure since in the prior art the voids are not formed in a controlled manner, and it is difficult to predict where the voids are formed.
Referring to FIG. 1b, an alternative prior art process is described. In this example the underlying insulation layer is planarized, and a thin layer of conformal interlevel dielectric 7 overlies the metal signal lines 11, 12, 13, 14, 15, 16 and insulation layer 44. The thin layer of conformal interlevel dielectric 7 produces large voids 25 and 26 in the interlevel dielectric. After these voids are filled with a flowable dielectric and the flowable dielectric is etched back, trenches are formed in voids 25 and 26. This presents a non-planar surface for the next interlevel structure, so subsequent interlevel structures have the same problems in forming controlled voids as the structure presented in FIG. 1a.
Additionally, in conventional processes, sealed voids are only formed in very narrow intermetal spacings with an aspect ratio greater than one, so only the capacitance in very narrow intermetal spacings is affected. Furthermore, there is a high probability that the void will be opened and contaminated in a later processing step. As determined in the present invention both of these problems stem from the proportional thickness of the dielectric to the width of the intermetal spacing. The thin layer of the dielectric overlying the metal signal lines also leads to the thickness of the interlevel dielectric above any void, sealing it, to be very small.
Referring now to both FIGS. 1a and 1b, if the flowable dielectric is SOG, and it is exposed toward the bottom of the vias formed in the interlevel dielectric, if aluminum 27 is used to fill the via a poisoned via may result. Although titanium, titanium nitride, titanium tungsten or a combination thereof 28 is usually deposited in the via to form a liner layer, when the liner layer is sputter deposited the liner may be very thin toward the bottom on the via. SOG exposed at the bottom of the via will not be contained by liner and will outgas, causing a poisoned via.
Referring now to FIG. 2, an alternative prior art integrated circuit is described. Metal signal lines 31, 32, 33, 34 and 35 overlie an insulation layer 44. The interlevel dielectric is deposited using high density plasma (HDP), a simultaneous deposit and etch process, to fill the entire intermetal spacing, typically without creating any voids. Using HDP and a typical dielectric material, voids will most likely not form in intermetal spacings having a width 0.25 .mu.m and above, and an aspect ratio of 3 or below.
It is therefore an object of this invention to provide a method of forming voids between conductive lines in a controlled and reliable manner.
It is a further object of this invention to provide a method of forming voids between conductive lines and yet presenting a planar, void-free surface for a subsequent layer of metallization.
It is a further object of this invention to provide a method such that all voids formed in intermetal spacings greater than a threshold width are exposed and filled with a flowable dielectric, and all voids formed in intermetal spacings of less than, or equal to, a threshold width are sealed.
It is a further object of this invention to provide a method such that all voids formed in intermetal spacings are exposed and filled with a flowable dielectric.
It is a further object of this invention to provide a method such that interlevel capacitance is reduced.
It is a further object of this invention to provide a method to increase the speed of an integrated circuit where the width of the intermetal spacings between metal signal lines are smaller than a threshold width.
It is a further object of this invention to provide a method to reduce RC delay in an integrated circuit due the width of the intermetal spacings between metal signal lines being smaller than a threshold width.
It is a further object of this invention to provide a method to reduce the possibility of poisoned vias.
It is a further object of this invention to provide such a method that utilizes conventional process flows.
It is further an object of the present invention to provide an integrated circuit formed according to such a method.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.